This invention relates in general to complementary metal-oxide-semiconductor (CMOS) integrated circuits, and in particular to a fast propagation technique in CMOS circuits using skewed logic.
A typical CMOS inverter includes a P-channel (PMOS) pull-up transistor and an N-channel (NMOS) pull-down transistor. Because PMOS is inherently weaker than NMOS, the size (i.e., channel width) of the PMOS pull-up transistor is usually made approximately 1.5 times larger than the NMOS pull-down transistor in order to minimize signal propagation time through a cascaded pair of inverter stages. Signal propagation delay time for a CMOS gate increases linearly with the fanout F of that gate. The fanout F for a given stage is defined by the ratio of the size of the load device (i.e., stage being driven) divided by the size of the driver stage. The larger the size of the transistors in a CMOS inverter, the faster the output can switch any given capacitive load. To drive a very large load with minimum delay, normal CMOS logic conventionally uses a chain of serially connected inverters that progressively grow in size, each stage having a fanout F of about three. Designing with a fanout of either lower or higher than three increases the delay to achieve a given required total fanout. At lower fanout per stage, too many stages are required, while at higher fanout per stage the delay per stage becomes excessive. Propagation delay time continues to be a critical design factor.
In some synchronous circuit applications it is possible to appreciably increase the signal propagation speed by using a technique known as post charge logic. As fully described in U.S. Pat. No. 4,985,643, post charge logic achieves much higher speed than that obtainable with normal CMOS logic circuits, and somewhat higher speed than that obtainable by the technique of the present invention. However, post charge logic has several limitations. It requires numerous feedback reset paths causing circuit layout problems. It also requires a reset time interval after each active pulse, before another pulse can be propagated. This limits the duty cycle on any pulse to 50% or less, which can be a severe limitation for many circuits including memory circuits. With a duty cycle limited to 50%, only one half of a cycle is available to develop a signal from a memory cell during a read cycle, or to force new data into a memory cell during a write cycle.
Thus, there remains a need to reduce propagation delay times in CMOS logic circuits without the limitations of post charge logic.